Vertical conduction MOSgated devices are well known. By MOSgated device is meant a MOSFET, IGBT or the like. By a vertical conduction device is meant a device in which current conduction through the die is from one surface of the die, through the thickness of the die, and to its opposite surface. By die is meant a single die or chip which is singulated from a wafer in which all die within the wafer are simultaneously processed before singulation. The terms die, wafer and chip may be interchangeably used.
FIG. 1 shows a known type of vertical conduction MOSFET, using a trench type technology. FIG. 1 is a cross-section through a MOSFET die and shows one cell of a device in which a plurality of identical such cells are laterally disposed relative to one another. These cells may be parallel stripes, or closed cells of circular, rectangular, square, hexagonal or any other polygonal topology and may appear identical in a cross-sectional view.
In FIG. 1, the wafer or die has an N+ substrate 20 of monocrystalline silicon (float zone, for example) which has a top epitaxially grown N type silicon layer, which includes drift region 21. A P type base implant and diffusion into the epitaxial layer forms the P base region 22, and an N type implant and diffusion forms the N+ source region layer 23. Spaced trenches 24 and 25 (which may be striped or cellular) are formed in the top of the wafer. A silicon dioxide or other insulation liner has a thick bottom section 30 and a thin vertical gate section 31 which receive a conductive polysilicon gate electrode 32. A top oxide segment 33 completes an insulated enclosure for gate polysilicon 32. A source electrode 40 is then deposited atop the wafer or chip and fills trench 24 to short the N+ source 23 to the P base, thereby to disable the parasitic bipolar transistor formed by regions 21, 22 and 23. A conductive drain electrode 41 is formed on the bottom of the die.
In operation, the application of a gate turn-on potential to gate 32 relative to source 40 will invert the concentration at the surface of P base 22 which lines oxide 31, thus permitting the flow of majority carriers from drain 41 to source 40.
It would be very desirable for many applications to reduce the capacitance between the gate and drain and the Qg and Qsw and to reduce the on resistance RDSON and gate resistance of the MOSgated device die of FIG. 1. It is also desirable to provide a MOSgated die structure which can be packaged in a variety of housings and can be copacked in a package with other die with reduced package resistance, minimal stray inductance, and good heat sinking capability.